1. Field of the Invention
The present invention relates to a phase-locked loop circuit.
2. Description of Related Art
A PLL (phase-locked loop) circuit is one of the most popular clock generating circuits. FIG. 7 shows a PLL circuit disclosed in FIG. 1 of International Patent Publication No. WO 99/19987. This PLL circuit includes a phase frequency detector (PFD) 14, a loop filter 18, a voltage controlled oscillator (VCO) 20, a clock divider 22, a decision circuit 30, and a control unit 32. In this PLL circuit, an input signal is input to the PFD 14. The PFD 14 generates a signal based on both the input signal and a feedback signal from an output side of the VCO 20, and outputs the generated signal to the loop filter 18. Then, the VCO 20 outputs the output signal based on a control voltage which is output from the loop filter 18. The output signal is fed back to the PFD 14 through clock divider 22.
Further, the decision circuit 30 detects the control voltage in this PLL circuit shown in FIG. 7. Based on a decision of the decision circuit 30, the control unit 32 decides a dividing ratio of the clock divider 22. A similar art is disclosed in Japanese Unexamined Patent Application Publication No. 09-191247.